Appeal No. 2004-0550
Application No. 09/802,201
doped p+ type rather than the n-type of the source and drain
regions (Answer, page 5, citing Figure 1 and col. 2, ll. 33-49).
The examiner applies Draper for the teaching to configure the
capacitor as a supply decoupling capacitor by coupling a
polysilicon gate 106 to a positive supply rail 114 and coupling
source and drain regions 112 to a ground potential 116 (Answer,
page 5). From these findings, the examiner concludes that it
would have been obvious to one of ordinary skill in this art to
use the p+ type polysilicon gate of Lee in the method of Rajkanan
“in order to make measurements of the characteristics of the gate
oxide as taught by Lee in column 2, lines 35-37.” Id. The
examiner also concludes that it would have been obvious to use
the couplings taught by Draper in the method of Rajkanan and Lee
“in order to increase the net carrier concentration in the device
region beneath the polysilicon gate as stated in column 4, lines
53-58 of Draper.” Id. We agree.
Appellants agree with the examiner that Rajkanan provides no
teaching or suggestion of forming a p+ type polysilicon gate on
the dielectric layer, where the source and drain regions are
doped n-type (Brief, page 6). Appellants argue that Lee does not
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