Appeal No. 2004-0748 Page 10
Application No. 09/427,226
that each die accesses the carrier substrate for commonly-required functions
commonly and discrete functions individually. It is contemplated that dice to be
employed in a stack may have the same or different components but a common
via layout for easy superimposition. The overall circuit defined by the die stack
may then be customized by the number and type of die employed and the use of
laser-blown or electrically-blown fuse elements, as known in the art, incorporated
in the die circuitry of each die. Thus, a via stack may be electrically connected to
components at one die level, but not at those above or below, serving only at the
other (unconnected) die levels as a bypass conductor.
Figures 1A, 1B and 1C of Farnworth depict an exemplary silicon die 10 with
exemplary conductive vias 12 and 14. An epitaxial layer 20 is formed on active side 16.
Active devices1 22 are superimposed on or immediately adjacent via 12. Passive
devices2 23 (see Figure 3) may similarly be formed on die 10.
Figure 4 of Farnworth depicts an eight-die stack including dice 210a, 210b, 210c,
210d, 210e, 210f, 210g, and 210h mounted on and electrically connected to a carrier
substrate 230. As can be seen schematically, a series of common-access via stacks
212a, 212b, 212c, 212d and 212e extend vertically through all eight dice and are
accessed by each. A second series of discrete access via stacks 214a, 214b, 214c,
214d, 214e, 214f, 214g, and 214h provide an individual chipselect function to each die
1 Active devices may include any such devices known in the art such as diodes, transistors, and
memory (ROM, PROM, EPROM, EEPROM, bubble, DRAM, SRAM) including subcomponents such as
transistors, capacitors and fuses.
2 Such as resistors, capacitors, fuses, etc.
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007