Appeal No. 2004-0748 Page 12
Application No. 09/427,226
In this rejection (final rejection, pp. 3-4) the examiner ascertained that Farnworth
does not disclose (1) building a first IC chip by installing the first die in a first package;
(2) building a second IC chip by installing the second die in a second package; and
(3) sealing the packages. The examiner then concluded that it would have been
obvious at the time of the invention to a person of skilled in the art to use the packaged
dies of Burns with the method of making a stacked device of Farnworth "in order to
easily electrically interconnect the individual packages using the lead frame leads, while
also utilizing a sealed device."
The appellants argue (brief, pp. 5-6) that the applied prior art does not suggest
the claimed subject matter. We agree. In our view, Burns provides no suggestion,
teaching or motivation for a person of ordinary skill in the art at the time the invention
was made to have modified Farnworth to arrive at the claimed invention. In that regard,
Farnsworth, as noted above, is directed to bare die configurations and stacked
multi-chip (bare die) assemblies with chip-integral vertical connection circuitry while
Burns, as noted above, is directed to four TSOP integrated circuit packages 22 stacked
together, and we discern no reason to combine these disparate teachings together.
Obviousness is tested by "what the combined teachings of the references would have
suggested to those of ordinary skill in the art." In re Keller, 642 F.2d 413, 425, 208
USPQ 871, 881 (CCPA 1981). But it "cannot be established by combining the
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