Appeal No. 2006-2407
Application No. 09/802,857
Independent claim 13 is reproduced below:
13. A data processing apparatus performing predetermined data processing
in accordance with instruction codes read from a program memory storing a
program, the data processing apparatus comprising:
a debugging circuit having a plurality of bug address setting registers and a
plurality of coincidence detecting circuits,
one of said plurality of bug address setting registers holding one of a
plurality of bug addresses that show the start of a buggy part of said program stored
in said program memory,
one of said plurality of coincidence detecting circuits comparing a program
address for reading instruction codes from said program memory with said one of
said plurality of bug addresses held in said one of said plurality of bug address
setting registers, said one of said plurality of coincidence detecting circuits
outputting one of a plurality of coincidence signals when said program address and
said one of said plurality of bug addresses coincide,
another of said plurality of bug address setting registers holding another of
said plurality of bug addresses that show the start of another buggy part of the
program stored in the program memory,
another of said plurality of coincidence detecting circuits comparing said
program address for reading instruction codes from said program memory with said
another of said plurality of bug addresses held in said another of said plurality of
bug address setting registers, said another of said plurality of coincidence detecting
circuits outputting another of said plurality of coincidence signals when said
program address and said another of said plurality of bug addresses coincide; and
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