Appeal No. 2006-2407
Application No. 09/802,857
The teachings of Hosotani are also compelling of the obviousness of the
claimed subject matter. The most pertinent figures appear to be those in figure 2, 4,
6 and 10. There is also an explicit statement at column 4, lines 57 through 59 to be
able to correct plural system bugs. The operation of the OR gate in these figures
which results from a match circuit/coincidence circuit output from subcircuits 9a-
9c, as well as the operation of the switch/connection control 10, provides a selective
output from one or plurality of bugs detected to the data bus 5 which feeds directly
to the CPU 1 in figure 2, for example, of Hosotani. The effective functionality of
this reference appears to be consistent with the modified teachings of the second
embodiment showing in figure 3 of Sagane.
Appellants’ remarks at pages 11 and 12 of the principal brief on appeal
therefore do not argue against the combinability of Sagane and Hosotani within 35
U.S.C. § 103. Notwithstanding this observation anyway, it appears to us that the
artisan would have found it obvious to have combined the teachings of both
references within 35 U.S.C. § 103 to provide an optimized approach to addressing
the situation of a plurality of bugs in a programming sequencing operation for a
CPU.
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