Ex Parte Slobodnik et al - Page 2

               Appeal 2007-0576                                                                             
               Application 10/025,816                                                                       
                                               A. INVENTION                                                 
                      The invention at issue on appeal concerns self-testing of memories.                   
               Memories sometimes feature built-in self-test ("BIST") mechanisms for                        
               conducting self-tests to detect any memory defects.  Because defects may                     
               vary from design to design and may vary with different fabrication processes                 
               applied to the same design, explain the Appellants, self-test methodologies                  
               are selected and tuned to a particular design and fabrication technique by the               
               concerned manufacturer.  A manufacturer will typically have a preferred test                 
               methodology that experience has taught is well suited to its particular                      
               environment.  The test methodology adopted by one manufacturer, however,                     
               may not work for another manufacturer.  (Specification 2.)                                   

                      By varying address sequencing, in contrast, the Appellants'                           
               programmable self-test controller allows different test methodologies to be                  
               performed.  (Id. 3.)  Their self-test controller can handle the different test               
               requirements of different manufacturers or the different test requirements                   
               that may arise for a single manufacturer as it develops its fabrication                      
               processes.  (Id. 3-4.)                                                                       

                      Claim 1, which further illustrates the invention, follows:                            
                      1. Apparatus for processing data, said apparatus comprising:                          
                            at least one memory having a plurality of memory                                
                      storage locations associated with respective memory addresses;                        
                      and                                                                                   
                            a self-test controller operable to control self-test of said at                 
                      least one memory; wherein                                                             



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