Appeal 2007-0576
Application 10/025,816
ABIST test." (Col. 4, ll. 31-33.) "These 9 bits are divided into 5 fields:
three bit Pointer field 14, one bit Address Increment field 15, three bit Data
Control field 16, one bit [Read/]Write Control field 17, and one bit End-Of-
Address-Space control field 18." (Id. ll. 33-37.)
In the Examiner's aforementioned example, we agree with him that
because Lo's Array Address Pointer field 14 contains "010,'' the ABIST
would perform the aforementioned steps "repeatedly . . . until the address
space has been fully explored. . . ." (Answer 13.) Because the Read/Write
Control field 17 contains a "1'' in the Examiner's example, however, the
exploration would be limited to writing. (Lo, col. 11, ll. 36-37.) Without
being able to read, in addition to write, the sequence of procedures specified
by the Examiner's "010100011" instruction cannot perform a test. At best,
the instruction would only enable preparing for a test. We agree with the
Appellants that "[s]ubsequently, a second 9-bit word will be needed with
read/write control field 17 set to '0', i.e., in the 'Read mode' so that the array
under test can be read to see whether the information which was previously
set in under the 'write mode' is correct." (Reply Br. 3.)
The absence of a single instruction specifying a sequence of testing
procedures negates anticipation. Therefore, we reverse the anticipation
rejection of claims 1 and 18 and of claims 2-9, 13, 16, 17, 19-26, 30, 33, and
34, which depend therefrom.
"In rejecting claims under 35 U.S.C. Section 103, the examiner bears
the initial burden of presenting a prima facie case of obviousness." In re
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