Appeal 2007-0576
Application 10/025,816
said self-test controller is responsive to a self-test
instruction specifying a test methodology to be applied to
perform at least one memory access to each memory location
within a sequence of memory storage locations, memory
address changes between successive memory locations accessed
within said sequence of memory storage locations being
selected in dependence upon said self-test instruction such that
said self-test controller may be configured by said self-test
instruction to implement different memory test methodologies.
B. REJECTIONS
Claims 1-9, 13, 16-26, 30, 33, and 34 stand rejected under 35 U.S.C. §
102(b) as anticipated by U.S. Patent No. 5,661,732 ("Lo"). Claims 10, 11,
14, 27, 28, and 31 stand rejected under 35 U.S.C. § 103(a) as obvious over
Lo and U.S. Patent Application Pub. No. 2003/0167428 ("Gold").
Claims 12, 15, 29, and 32 stand rejected under § 103(a) as obvious over Lo
and U.S. Patent No. 6,001,662 ("Correale").
III. PROCEDURAL MATTER
The Evidence Appendix of an Appeal Brief shall "contain[ ] copies of
any evidence submitted pursuant to §§ 1.130, 1.131, or 1.132 of this title or
of any other evidence entered by the examiner and relied upon by appellant
in the appeal, along with a statement setting forth where in the record that
evidence was entered in the record by the examiner." 37 C.F.R.
§ 41.37(c)(1)(ix) (2005).1 Here, although the Appellants rely on the
"definition of methodology . . . contained in Webster's 9th New Collegiate
1 We cite to the version of the Code of Federal Regulations in effect at the
time of the Appeal Brief.
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