Appeal 2007-2218
Application 10/035,595
Appellant invented systems and methods for performing floating point
operations, and more particularly systems and methods for performing
floating point addition with embedded status information associated with a
floating point operand. (Spec. [002]).
Representative independent claim 1 under appeal reads as follows:
1. A system for providing a floating point sum, comprising:
an analyzer circuit configured to determine a first status of a
first floating point operand and a second status of a second floating
point operand based upon data within the first floating point operand
and data within the second floating point operand respectively; and
a results circuit coupled to the analyzer circuit and configured
to assert a resulting floating point operand containing the sum of the
first floating point operand and the second floating point operand and
a resulting status embedded within the resulting floating point
operand.
The Examiner rejected claims 1-5 and 7-40 under 35 U.S.C. § 102(b).
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Huang US 5,995,991 Nov. 30, 1999
The Examiner also rejected claims 1-5 and 7-40 under 35 U.S.C.
§ 103(a).
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Lynch US 6,009,511 Dec. 28, 1999
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