Appeal 2007-2218
Application 10/035,595
9. In the conventional circuit, when the result of an arithmetic
operation is zero, the arithmetic section outputs selector control signals to
the multiplexers 222 and 224 for selecting the eight ‘0’ bits for the exponent
and twenty-three ‘0’ bits for the magnitude. (col. 3, ll. 66-67, and col. 4,
ll. 1-4).
10. FIG. 3 shows a conventional detector 24 or 26. As shown, the
detector 24 or 26 includes two comparator circuits 252 and 254. (Col. 4,
ll. 24-26).
11. In the conventional circuit, three AND gates 261, 262 and 263
are also provided. The AND gate 261 receives as inputs the logic bits
outputted on the lines 255 and 257. The AND gate 261 therefore outputs a
signal indicating whether or not the operand represents a zero valued special
operand. (Col. 4, ll. 41-45).
12. The prior art Lynch patent describes that the “FPU [floating
point unit] core uses the tag value associated with an operand to determine
whether the tag value is a special floating point number.” (Col. 16,
ll. 62-65).
PRINCIPLES OF LAW
On appeal, Appellant bears the burden of showing that the Examiner
has not established a legally sufficient basis for anticipation based on the
Huang patent.
Appellant may sustain this burden by showing that the prior art
reference relied upon by the Examiner fails to disclose an element of the
claim. It is axiomatic that anticipation of a claim under § 102 can be found
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