Appeal 2007-2218
Application 10/035,595
numerical value of the operand (claims 10 and 12) or indicates what the data
within the operand will represent (claims 9, 11, 13, and 14).
35 U.S.C. § 102
Appellant correctly points out that the device of figure 4 of Huang
does not produce “a resulting floating point operand containing the sum of
the first floating point operand and the second floating point operand and a
resulting status embedded within the resulting floating point operand” as
required by claim 1. Contrary to the Examiner’s contention (Answer 14),
Huang’s “tag value” does not “constitute a teaching [of] data within the
floating point operand as claimed.” Rather, Huang discloses that the tag
(status info) stands separate from the operand (result). (FF 1 and 2).
However, Prior Art figures 1-3 of Huang teach all the features of
claims 1-5. See FF 3-11. Claim 1 – an analyzer circuit (items 24 & 26) and
a results circuit (items 14 & 22). Claim 2 – a first buffer (inherent to item 24
which receives and outputs), a second buffer (similarly inherent to item 26),
first operand analysis circuit (items 252, 254, & 261 of item 24), and second
operand analysis circuit (items 252, 254, & 261 of item 26). Claims 3 and 4
– memory storage (item 12). Claim 5 – an adder circuit (item 14, see FF 8),
an adder logic circuit (item 14, see FF 9), and a result assembler (item 22).
For the special case of addition of the “zero” operand plus the “zero”
operand to yield the “zero” operand, the conventional circuit corresponds to
the subject matter of Appellant’s claims 1-5. Thus, contrary to Appellant’s
ultimate contention, Huang does disclose the subject matter of claims 1-5.
9
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: September 9, 2013