Ex Parte Steele - Page 8

                 Appeal 2007-2218                                                                                        
                 Application 10/035,595                                                                                  


                                                     ANALYSIS                                                            
                                                 Claim Interpretation                                                    
                        Claim 1 recites an analyzer circuit configured to determine a first                              
                 status and a second status based on data within respective first and second                             
                 floating point operands.                                                                                
                        Claim 1 further recites a results circuit coupled to the analyzer circuit                        
                 and configured to “assert a resulting floating point operand containing the                             
                 sum of the first floating point operand and the second floating point operand                           
                 and a resulting status embedded within the resulting floating point operand.”                           
                        We interpret claim 1 as requiring at least: 1) a plurality of operands                           
                 each of which “containing” encoded status flag information, and 2) a result                             
                 circuit that produces a resulting floating point operand containing both a sum                          
                 (a result value) and status information.                                                                
                        The language of claim 1 does not preclude the sum and the status                                 
                 information from being represented by the same data within the resulting                                
                 floating point operand.  See FF 4 above for an example of a floating point                              
                 operand whose bits result in a value of “zero” and whose bit string has been                            
                 assigned a status of representing “zero.”1                                                              
                        As to claims 9-14, these claims fail to recite any structural or                                 
                 functional limitations.  Rather, each of these claims merely indicate the                               


                                                                                                                        
                 1 We note that claim 1 would distinguish over the cited prior art if the claim                          
                 were amended to require a single resulting floating point operand that                                  
                 contains distinct parts which represent a value and encoded status                                      
                 information.                                                                                            
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