Appeal No. 95-2218
Application 07/902,073
variable delay would have to use the same signal. The detecting
means would also be coupled with the VFO and the variable delay
means. The PLL in Fischler's VFO corresponds to the
"conventional" PLL that comprises Appellant's window generator.
Moreover, Fischler's PLL is coupled in series, and synchronized,
with the anticipator 62, which Appellant has conceded corresponds
to the claimed DRDSS circuit. Consequently, we conclude that the
combination of Pederson and Fischler, in the manner that the
references suggest, would meet the limitations in claim 12.
6. The phase shifting set forth in claim 15, which depends
from claim 12, is precisely corresponds to the phase shifting
caused by Pederson's variable delay circuit 22. (7:29-8:2.)
Consequently, we conclude that this function of the claimed
variable delay means does not distinguish the subject matter of
claim 15 from the proposed combination of Fischler and Pederson.
7. Claim 16, which depends from claim 12, requires the
window pulse generating means to comprise a PLL synchronized with
the DRDSS circuit. As we noted above, Fischler's VFO comprises a
PLL synchronized with an anticipator that corresponds to the
claimed DRDSS circuit. Consequently, this limitation does not
distinguish the subject matter of claim 16 from the proposed
combination of Fischler and Pederson.
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