Appeal No. 95-2218
Application 07/902,073
one-half cell delay, an anticipator, a variable bit cell delay, a
one-third cell delay and a delayed read data single shot (DRDSS).
(Paper 1 at 3, emphasis added.)
6. The window pulse generating means may comprise "a
phase-locked loop synchronized with said DRDSS-delayed data
pulse". (Claim 16, which depends from claim 12.) The disclosed
window generator "may comprise the phase locked loop included in
data separator 20". (Paper 1 at 28.) "The phase locked loop is
shown as a conventional PLL comprised of [voltage-controlled
oscillator] VCO 30, a frequency divider 32, a comparator 34, a
charge pump 38 and a filter 40, all interconnected in a loop."
(Paper 1 at 12.) "Microprocessor 42 is coupled to VCO 30 and is
adapted to supply a zone identifying signal to the VCO which acts
as a 'course' control." (Paper 1 at 13.)
B. The rejection
7. The examiner has rejected (Paper 9 at 3) claims 12-17
under 35 U.S.C. § 103 in view of:
Pederson 5,109,304 28 Apr. 1992
Fischler et al. (Fischler) 4,894,734 16 Jan. 1990
8. Claim 17 also stands rejected (Paper 9 at 6) under
35 U.S.C. § 103 in view of Pederson, Fischler, and
Tanaka et al. (Tanaka) 5,142,420 25 Aug. 1992
(filed 23 Apr. 1990)
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