Appeal No. 95-2218
Application 07/902,073
15. Fischler discloses (9:11-10:14) a variable frequency
oscillator (VFO) 12 that "is used to establish a decode window to
separate the data from the read channel." (9:45-46.) The VFO
includes an anticipator 62 (9:11-13) and a voltage control
oscillator (VCO) 65 (9:35-37; Fig. 3). The VFO is a PLL (9:59-
60), the phase of which is controlled by the anticipator (9:49-
53).
16. Fischler's PLL (Fig. 3) appears to be structurally
equivalent to the "conventional" PLL that comprises Appellant's
window generator. Fischler's PLL has a VCO 65, a frequency
divider 68, a comparator (dual-mode phase-frequency detector 63),
a charge pump 64, and a filter 77, connected in a loop.
(Fig. 3.) The output of filter 77 is the fine control signal.
(9:28-30.) The comparator also receives a reference signal FREF
(via anticipator 62) from a reference oscillator (VCO 86) except
during read operations. (8:61-9:19.) Fischler provides coarse
1(...continued)
takes up too much "real estate". (Paper 1 at 4-5.)
Nevertheless, Appellant has not drafted his claim so as to
exclude Fischler's anticipator. In re Morris, __ F.3d ___, ___,
43 USPQ2d 1753, 1759 (Fed. Cir. 1997) (Applicants bear the burden
of precisely claiming their inventions.). For instance,
Appellant did not use means-plus-function language to claim the
DRDSS circuit. Cf. Greenberg v. Ethicon Endo-Surgery Inc.,
91 F.3d 1580, 1584, 39 USPQ2d 1783, 1786 (Fed. Cir. 1996).
Moreover, Appellant has conceded the equivalence of Fischler's
anticipator to the claimed DRDSS circuit for the purposes of
appeal.
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