Appeal No. 96-1584
Application 08/066,697
The respective positions of the examiner and the appellant
with regard to the propriety of these rejections are set forth in
the final rejection (Paper No. 8) and the examiner's answer
(Paper No. 12) and the appellant's brief (Paper No. 11).
APPELLANT’S INVENTION
In FIG. 1 appellant discloses an integrated circuit
architecture wherein substrate 13 is coupled to receive a bias
V , the value of which is the same or close to the voltage
b
applied to the N- island 11. As a result, the voltage
differential across dielectric layer 15 is effectively zero so
that no electron/hole pairs will be induced at interface 27
between N- region 11 and region 25. This limitation on the
voltage differential between the island and substrate ensures
that the electric field generated as a result of the substrate
bias voltage is never high enough to cause avalanche generation
of electron/hole pairs at interface 27 so as to degrade the
breakdown voltage characteristic of the device at the PN junction
31.
FIGS. 2 and 3 are examples of trench-isolated island
integrated circuit architectures. In order to prevent
hole/electron pairs from being generated at the N-/N+
island/buried layer interface 27, which would degrade the
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