Appeal No. 94-3053
Application 07/832,661
and neither Hester nor d’Angeac discloses these claimed
features. Brief at 7.
In response, the Examiner states:
[i]t would have been obvious to a person
having ordinary skill in the art to provide
a scan string selection logic network in
accordance with the claims on the chip
disclosed by Hester, because d’Angeac
evidences the necessity of such logic.
Answer at 6. However, a review of d’Angeac fails to reveal
why a person of ordinary skill in the electronic processor art
would have reason to modify Hester’s support processor to
include circuitry for selecting particular sensor circuits in
the support
processor. We fail to find a teaching of an on-chip condition
sensor which includes a logic network connected to said sensor
circuits, said serial scan circuit being interconnected with
said logic network for determining selections of sensor
circuits by said logic network with the necessary reasons
found in the prior art to combine it with the support
processor of Hester. Therefore, we will not sustain the
Examiner's rejection of Appellants' claim 27.
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