Appeal No. 94-3053
Application 07/832,661
LSSD second latches serving as "condition
sensors", is addressable by a on-chip
addressing "logic network" 42-48 that
provides a "multiplexer having inputs
connected to said sensor circuits" for
"determining selections of sensor
circuits". LSSD latches 42-44 receive
"control bits". It would have been obvious
to a person having ordinary skill in the
art to provide a scan string selection
logic network in accordance with the claims
on the chip disclosed by Hester, because
d’Angeac evidences the necessity of such
logic,
answer at 6, and
[a]s the examiner’s answer indicates that
d’Angeac provides scan loop string
selection by a logic network 42-48 and the
examiner’s answer also indicates that
Hester provides a counter in the form of a
scannable control register IAR that can
have its’ data scanned
out and in, no further response is deemed
necessary,
supplemental answer at 2.
However, a review of the references relied upon
fails to reveal why a person of ordinary skill in the
electronic processor art would have any reason to modify
Hester’s circuitry to include "a multiplexer having inputs
connected to said sensor circuits and an output connected to
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