Appeal No. 95-4815
Application No. 08/065,387
Any type of non-consecutive addressing for memory
region 60 [of VRAM 30] must be performed by the
processor itself. Hence, although the data may be
distributed in non-consecutive addresses in RAM, it
was initially generated by the processor as non-
consecutively addressed data.
The examiner has pointed to nothing within the disclosure of
Diepstraten that would contradict this reading of the
reference. Clearly, if the non-consecutive addressing was
already performed by the processor, there would be nothing to
receive “the consecutive data field from the processor,” as
claimed.
Accordingly, we will not sustain the rejection of claim 1
under 35 U.S.C. ' 103.
However, when we consider claim 2, we reach an opposite
result. This claim does not require anything to receive a
consecutive data field from the processor. The graphics
processor 22, itself, in Diepstraten, may be both the means
for receiving a stream of data words with associated
consecutive addresses and the means for distributing that
stream of data words into VRAM at non-consecutive addresses.
With regard to the claim limitation of “evenly spaced
addresses,” we agree with the examiner’s reasoning, at page 5
of the answer, that Figure 2 of the reference clearly shows
the rows of region 60 within Diepstraten’s VRAM being evenly
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