Appeal No. 95-4815
Application No. 08/065,387
spaced in that there are 385 addresses between the first and
second rows and there are also 385 addresses between the
second and third rows.
Therefore, we will sustain the rejection of claim 2 under
35 U.S.C. ' 103.
With regard to claim 3, this claim contains the
requirement, as does claim 1, that something actually receives
the consecutive data field from the processor and distribute
it to non-consecutive addresses (in the case of claim 3, those
non-consecutive addresses are also evenly spaced). Therefore,
for the reasons supra, we will not sustain the rejection of
claim 3 under 35 U.S.C. ' 103.
With regard to claims 4 through 7, we will not sustain
the rejection under 35 U.S.C. ' 103 because the claims all
contain the limitation that the writing of character data into
video RAM be done “within 80 clock cycles…”
The examiner recognized that Diepstraten disclosed
nothing regarding the speed at which writing character data
into VRAM was performed but the examiner relied on Maruko for
the teaching of providing character data to a display memory
in the form of an 8 x 10 array of pixels. The examiner then
concluded that it would have been obvious to use the character
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