Appeal No. 1996-2195
Application 08/120,911
This is a decision on appeal from the final rejec-
tion of claims 39 through 44, 46 through 74, 77 and 78.
Claims 1
through 38 have been cancelled. On February 1, 1995, Appel-
lants filed an amendment after final which was entered into
the record. The amendment cancelled claims 52 and 77 and
amended claim 39. Therefore, claims 39 through 44, 46 through
51, 53 through 74 and 78 are properly before us for our
consideration on appeal.
The present invention relates to a processor with
cache memory used in a multiprocessor system. In particular,
the invention relates to a processor having a main cache and a
receive cache memory. The receive cache memory is for receiv-
ing data from other processors in the network. The processor
is able to read data from either the main cache or the receive
cache in parallel.
Independent claim 39 is reproduced as follows:
39. A processor for a multiprocessor system con-
nected to a network, comprising:
an instruction processor for executing instructions;
2
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