Ex parte HIGUCHI et al. - Page 3




          Appeal No. 1996-2195                                                        
          Application 08/120,911                                                      



                    a local memory for holding instructions to be exe-                
          cuted by the instruction processor and data to be processed                 
          thereby, and an access controller for controlling access to                 
          said local memory;                                                          
                    a main cache for holding part of data held by said                
          local memory and a main cache controller connected to said                  
          main cache and instruction processor, and said access control-              
          ler for controlling said main cache; and                                    



                    a sending unit connected to said main cache for                   
          sending data on the network and a receiving unit for receiving              
          data from the network;                                                      
                    a receive cache and a receive cache controller                    
          connected to said receive cache, said receive unit and said                 
          instruction processor and said access controller for control-               
          ling the receive cache so that said receive cache temporarily               
          stores data received by the receiving unit which is to be                   
          stored in said local memory;                                                
                    said main cache controller responding to a memory                 
          write request provided by said instruction processor for first              
          data to be written into the local memory, so as to write said               
          write data into said main cache,                                            
                    said main cache controller not writing said received              
          data into said main cache and said receive cache controller                 
          not writing said first data requested by said memory write                  
          request into said receive cache;                                            
                    said main cache controller and said receive cache                 
          controller both further responding to a common memory read                  
          request initiated by said instruction processor unit for                    
          second data held in said local memory so as to read the second              
          data requested by the read request from one cache which holds               

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