Appeal No. 1996-2195
Application 08/120,911
only the main cache with respect to writing the data and uses
both caches for reading the data. Thus, the CPU is allowed to
access receive data held in the receive cache directly without
reading the data from the local memory.
We note that this operation is claimed by
Appellants. For example, in claim 39, Appellants claim
said main cache controller and said receive
cache controller both further responding to
a common memory read request initiated by
said instruction processor unit for second
data held in said local memory so as to
read the second data requested by the read
request from one cache which holds said
second data among said main cache and said
receive cache.
In the only other independent claim, claim 53, Appellants
claim
means responsive to a memory read request
provided from the processing unit for read
out of second data from said local memory
for reading out the second data requested
by the memory read request from one of the
first and the second cache memories if said
one cache memory holds the requested second
data and for supplying the read second data
to said processing unit.
On page 5 of the answer, the Examiner states that
Watkins does not expressly teach the common memory read
request to both the central cache and the I/O cache as claimed
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