Appeal No. 1996-2195
Application 08/120,911
to operate. Segers discloses that the secondary cache memory
is configured with Dynamic Random Access Memory (DRAM) and the
primary cache memory is configured with Static Random Access
Memory (SRAM). The DRAM arrays allow for higher density but
sacrifice speed, while the SRAMs have faster access speed but
sacrifice density. Segers takes advantage of both of these by
providing one cache made up of DRAMs and the other cache made
up with SRAMs. However, Segers is not concerned with data
coherency between an I/O cache and a main memory cache.
In viewing Watkins and Segers, we fail to find that
the prior art suggests the desirability of modifying the
Watkins reference so as to destroy the data coherency by
allowing the CPU to access both the I/O cache and the main
memory cache simultaneously. Therefore, we will not sustain
the Examiner's rejection of Appellants' claims under 35 U.S.C.
§ 103.
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