Appeal No. 1996-2369 Page 3
Application No. 08/191,723
In addition, data stored in the CPU’s result buffer had to be
temporarily stored elsewhere and, upon executing the next
write instruction, retrieved for transfer to the LCD’s
segment-drive circuit. Such processing burdened the CPU.
Successive execution of read instructions produced a similar
problem. The appellants’ invention employs a loop count
register to reduce the burden and speed the display.
Claim 1, which is representative for our purposes,
follows:
1. A display control circuit which causes display
to be performed on a display means having a display
space in which addresses are set, by supplying to
the display means address data of a first number of
bits corresponding to the display capacity of the
display space, comprising:
data regulating means which receive the address
data of the first number of bits and which output
address data of a second number of regulated bits
comprising the first number of bits which have been
logically combined with a predetermined number of
extended bits, wherein when the address data of the
first number of bits are incorrect and are for a
display position outside the addresses in the
display space but which when unregulated may result
in an undesired display within the display space,
said data regulating means causing the address data
of the second number of regulated bits to be within
an addressing range outside the display space based
on the address data provided by said second number
of regulated bits, and
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