Ex parte INAMORI et al. - Page 8




          Appeal No. 1996-2369                                       Page 8           
          Application No. 08/191,723                                                  


          address data is [sic] ‘corrected’.”  (Id.)  The appellants                  
          conclude their argument as follows.                                         
              [T]he Examiner has failed to provide any reasonable                    
               basis as to why the artisan would have found it                        
               obvious to modify that which is acknowledged to be                     
               prior art in Figures 1 through 3 in such a manner as                   
               to arrive at that which is required in claim 1                         
               including a "data regulating means" and a "detecting                   
               means" ....  (Appeal Br. at 18.)                                       

          The examiner replies, “the difference between Appellant's                   
          device and the prior art is software and hardware.  One can                 
          combine two address data bits by hardware as Appellant can,                 
          the software of prior art (figures 1-3) can do the same                     
          function combining two address data bits as Appellant's                     
          device.”  (Examiner’s Answer at 12.)  We agree with the                     
          appellants.                                                                 


               Independent claim 1 specifies in pertinent part the                    
          following limitations:                                                      
                    data regulating means which receive the address                   
               data of the first number of bits and which output                      
               address data of a second number of regulated bits                      
               comprising the first number of bits which have been                    
               logically combined with a predetermined number of                      
               extended bits, wherein when the address data of the                    
               first number of bits are incorrect and are for a                       
               display position outside the addresses in the                          







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