Appeal No. 1996-2369 Page 13
Application No. 08/191,723
Independent claim 8 specifies in pertinent part the
following limitations:
hardware conversion means responsive to said
address data bits and said means for detecting for
logically converting said address data bits to new
address data bits within an extended addressing
range beyond said maximum effective display space so
as to prevent the occurrence of the undesired
display at an addressable position within said
maximum effective display space of the display
means,
said hardware conversion means including logic
circuit means for producing and logically combining
a predetermined number of extended address data bits
with said received address data bits for producing
said new address data bits.
Giving the claim its broadest reasonable interpretation, the
limitations recite a logic circuit means for producing and
logically combining a predetermined number of extended address
data with received address data.
The examiner fails to show a teaching or suggestion of
these limitations in the prior art. Citing page 3, line 23,
through page 4, line 6, of the appellants’ specification, the
examiner asserts that the admitted prior art taught therein
“teaches a conversion means responsive to the address data and
means for
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