Appeal No. 97-1246 Page 2
Application No. 08/196,731
BACKGROUND
The appellants’ invention involves detecting and
reporting errors in a single-chip microprocessor. The
invention detects memory faults by checking the parity of data
read from memory (i.e., cache, translation look-aside buffer)
built-in to the chip. The invention also detects bus faults
by checking the parity of addresses detected during bus
snooping. When a memory fault or a bus fault is detected the
invention outputs a processor error signal to the outside of
the chip to indicate occurrence of the fault. In addition,
the invention helps recovery from errors by generating and
storing data that identifies specifically errors occurring
during access of an external bus.
Claims 1, 4, and 5, which are representative of the
invention, follow.
Claim 1. A one-chip microprocessor, comprising:
instruction executing means for executing instructions;
storing means, accessible during instruction execution by
said instruction execution means, for storing a plurality of
data and parities corresponding to respective data; and
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