Appeal No. 97-1246 Page 3
Application No. 08/196,731
parity generating and checking means, which is connected
to said storing means, for, when data is read from said
storing means as part of instruction execution of said
instruction executing means, comparing the stored parity of
the data which has been read, with the parity of the data
which has been read to generate a parity error signal when
they do not agree;
wherein, when said parity generating and checking means
generates said parity error signal, said instruction executing
means suspends the instruction execution and outputs a signal
to outside the chip to inform of an occurrence of error.
Claim 4. A one-chip microprocessor, comprising:
an instruction execution unit executing instructions;
a cache memory which is accessible during instruction
execution by said instruction execution unit;
an internal address bus;
address inputting means for inputting addresses from
outside the chip and outputting them to said internal address
bus;
address parity inputting means for inputting address
parities from outside the chip;
bus snooping means, to which an invalidating request
signal of said cache memory is inputted from outside the chip,
for snooping said internal address bus and outputting a
predetermined signal when an address outputted to said
internal address bus is an address to be invalidated; and
parity checking means, which is connected to said
internal address bus and said address parity input means, for,
when a predetermined signal is outputted from said bus
snooping means, checking the address parity outputted to said
internal address bus, and generating a parity error signal
when detecting a parity error;
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Last modified: November 3, 2007