Appeal No. 97-1246 Page 10
Application No. 08/196,731
Amini were integrated onto a single chip, there would be a
need to output a signal off the chip.
Also regarding claim 5, the appellants argue that Amini
does not disclose holding information indicating whether an
object to be accessed is an instruction or data and
information indicating whether a memory management unit
accesses an address translation table. (Brief, p. 11) We
agree that the Examiner failed to show that Amini discloses
these features. The section of Amini cited by the Examiner,
(Examiner’s Answer, p. 8), as teaching the holding of
information indicating whether an object to be accessed is an
instruction or data, viz., col. 8, lines 54-68, instead
discloses holding an address and time of a parity error. The
examiner’s allegation that it would have been obvious to
store address translation table information in a status
register, (Examiner’s Answer, pp. 8-9), is irrelevant because
it concerns holding translation information rather than
information indicating whether a memory management unit
accesses an address translation table as claimed. For these
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