Appeal No. 97-1246 Page 4
Application No. 08/196,731
wherein, when said parity checking means generates said
parity error signal, said instruction execution unit suspends
instruction execution and outputs a signal to outside the chip
to inform of an occurrence of error.
Claim 5. A one-chip microprocessor, comprising:
an instruction execution unit executing instructions;
a memory which is accessible during instruction execution
by said instruction execution unit;
a memory management unit performing address translation
by referring to an address translation table of an instruction
from said instruction execution unit;
a bus access control unit performing external bus access
by request from said instruction execution unit or said memory
management unit;
error detecting means for detecting an abnormal bus
access generated as a result of bus access by said bus access
control unit, and generating different error signals
corresponding to kinds of resulting abnormal bus access;
a status register which is connected to said bus access
control unit, storing a kind of bus access being executed; and
an error register, which is connected to said error
detecting means and said status register, holding error
information;
wherein said bus access control unit, when starting the
bus access, holds
information indicating whether the bus access is a read
access or a write access,
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Last modified: November 3, 2007