Appeal No. 98-1396
Application 08/300,666
(Figure 5: A, note the previous pixel numbers being stored), being input in parallel with the
first ROM (note the parallel input of Figure 5: B and A);[l]atch means to which the ROMs
are output (Figure 6: 25 and 27)." (See Answer at page 6, paragraph 2.) From a review
of Hackett, it is clear that Hackett discloses "registers" A and B which temporarily store
data input thereto. (See col. 6.) This data is then processed by the subtractors. This is
not the same as a "second ROM R-2 for similarly storing previous pixel values, being input
in parallel with first ROM R-1" as set forth in claim 23. Furthermore, Hackett does not
teach the input of the current pixel value to a prescribed address in a first ROM. The
registers of Hackett are not disclosed as being addressed in the functioning of the scaler.
Hackett discloses that the registers are input the number of needed pixels. Alternatively,
the claimed invention sets forth that the
"current pixel value is input to a prescribed address in said first ROM." It is clear that the
pixel data forms part of the address for addressing the new pixel data which is
already stored in the ROM. The ROMs set forth in the claims do not receive data
values and store them as Hackett discloses. This is significant since the ROM is Read
Only Memory. The ROMs store the pixel data and are addressed using the current pixel
values. Moreover the subtractors disclosed by Hackett do not perform the addition
mapping as recited in the language of the claim.
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