Appeal No. 2000-1356 Application 07/979,772 The invention is related to a data processing system and method wherein the speed of execution of instructions can be increased by executing a plurality of instructions in parallel wherever possible. The unique features of the invention lie in the inclusion of a conflict detector, a cache memory, a first mask and a second mask. The conflict detector evaluates each of a plurality of instructions input to the instruction unit so as to determine conflicts within the plural instructions. When conflict is detected by the conflict detector, an indication of the conflict is stored in the cache along with the plural instructions. The conflict information is used to control the sequence of feeding the instructions to the first mask and the second mask. If a conflict is detected, then one of the instructions is executed in parallel with a NOP instruction by the first and second arithmetic operation units. If no conflict is detected, then the plural instructions are executed in parallel by the first and second arithmetic units. The invention is further illustrated by the following claim below. 38. A processor system, comprising: -2-Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NextLast modified: November 3, 2007