Appeal No. 2000-1356
Application 07/979,772
it obvious to employ additional arithmetic logic units to the
processor of Lee to enhance the processing speed. Therefore,
we sustain the obviousness rejection of claim 182 over Lee.
Claim 92
Claim 92 further adds to claim 91 the limitation of
“parallel processing said at least two instructions ...
without conflict.” This limitation was discussed in regard to
claim 48 above. Therefore, for the same rationale as claim 91
and claim 48, we sustain the obviousness rejection of claim 92
over Lee.
Independent claims 120, 130, 138, 173 and 174, and their
dependent claims
These independent claims each contains a limitation equal to,
or similar to, the limitation of “a state of said plurality of
instructions and information remaining in said cache memory
after output of said plurality of instructions is the same as
the state of said plurality of instructions and information
before output of said plurality of instructions” (claim 120).
We do not find, and neither has the Examiner specifically
identified, any discussion in Lee regarding the above
limitation. Therefore, we
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