Appeal No. 2000-1356
Application 07/979,772
[t]here is no teaching ... in Lee regarding ... the parallel
processing of the instructions when the information indicates
that the instruction[s] can be processed in parallel without
conflict.” We are persuaded by the Examiner’s position
[answer, pages 7 to 10] that the information in cache 112 of
Lee includes the information resulting from the resolution of
the potential conflict in the processing of a branch
instruction, and this information is outputted at 122A and
122B in a parallel manner to processor 116. Therefore, we
sustain the obviousness rejection of claim 48 over Lee.
With respect to the dependent claims 49, 50, 51, 52, 53
and 55 (keeping in mind that the phrase “a predetermined
number of bits” corresponds to the phrase “a single bit”),
they
respectively include the limitations corresponding to the
limitations included in the dependent claims 42, 43, 44, 45,
46 and 47 which have been discussed above. Therefore, for the
rationale of claim 48 and the noted respective dependent
claims, we sustain the obviousness rejection of claims 49, 50,
-9-
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