Appeal No. 1997-2247 Page 2
Application No. 08/259,798
thousands of word lines of the memory typically have been
asserted at a time and only half of the bit lines, i.e.,
either the true or complement bit lines, of the memory
typically have been driven to a desired voltage level at a
time, such testing has proven time consuming.
The invention speeds stress testing of an IC memory.
Specifically, a control signal is applied to the necessary
predecoders and row factor generators to enable all word lines
of the memory simultaneously. The signal is also applied to
disable the sense amplifiers of the memory. In addition, all
bit lines, i.e., both the true and complement bit lines, of
the memory are initialized as the control signal clamps a bit
line voltage reference to a Vss voltage. These operations
effectively write zeros across the whole memory at once and
provide a proper bias on the cells of the memory for testing.
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