Appeal No. 1997-2247 Page 3
Application No. 08/259,798
Claim 1, which is representative for our purposes,
follows:1
1. A circuit comprising:
an array of storage cells arranged in rows and
columns;
a plurality of wordlines, each wordline
connected with gates of transfer transistors of a
different row of the storage cells;
a node for receiving a supply voltage;
a decoder, responsive to a control signal, for
simultaneously applying the supply voltage to all of
the wordlines of the array.
The references relied on in rejecting the claims follow:
Hardee et al. (Hardee) 4,680,762 July 14, 1987
Kuo et al. (Kuo) 5,034,923 July 23, 1991.
Claims 1-4 stand rejected under 35 U.S.C. § 103 as obvious
over Hardee. Claims 5-9 and 12 stand rejected under 35 U.S.C.
§ 103 as obvious over Hardee in view of Kuo. Claims 10 and 11
stand rejected under 35 U.S.C. § 103 as obvious over Kuo.
Rather than repeat the arguments of the appellant or examiner
in toto, we refer the reader to the brief and answer for the
respective details thereof.
1The copy of claim 1 that appears in Appendix A of the
brief is inaccurate.
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