Ex parte NISHIMURA et al. - Page 14




            Appeal No. 1997-2983                                                   Page 14               
            Application No. 08/482,792                                                                   


            temporarily saved in another location (usually, an external                                  
            memory), and data necessary for the different program must be                                
            newly read from the outside and set in the registers."  (Spec.                               
            at 1.)  Both Levy and Delagi, moreover, teach using a                                        
            dedicated bus to transfer data between a CPU and a memory.                                   
            Levy specifically mentions "a fast memory 73, which is coupled                               
            to the central processing unit 60 through dedicated bus 74."                                 
            Col. 6, ll. 5-6.  For its part, Delagi specifically discloses                                
            that "[a] second port 8 of the high speed memory 7 is coupled                                
            directly to the arithmetic and logical unit 9 of central                                     
            processor 2 by a high speed dedicated bus 10."  Col. 2, ll.                                  
            44-47.  Persons skilled in the art, moreover, would have known                               
            that the central processing unit of Levy and the central                                     
            processor of Delagi include registers to and from which data                                 
            are transferred.                                                                             


                  When the teachings of Levy and Delagi of using a                                       
            dedicated bus to transfer data between a CPU and a memory were                               
            combined with the teaching of AAPA to transfer data between a                                
            register in a CPU and a memory, the result would be a                                        








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