Appeal No. 1997-2983 Page 8
Application No. 08/482,792
Claims 1-4, 6-12, and 14
Claims 1-4 and 7-12 specify in pertinent part the
following limitations: "third and fourth buses being
exclusively used for switching between the presently executing
program and the different program ...." Similarly, claim 6
specifies in pertinent part the following limitations: "a
third bus for connecting said CPU with said RAM, said third
bus being used only for passing data respectively held in said
Program Counter Register, said Processor Status Word Register,
and said General Purpose Register Set between said CPU and
said RAM, ... a fourth bus for connecting said CPU with said
RAM and passing address data corresponding to said data passed
through said third bus....." Also similarly, claim 14
specifies in pertinent part the following limitations:
a) executing a first program using said
execution unit of said microcomputer, wherein said
execution of said first program uses a processor
status word, a program counter value and a register
bank corresponding to said first program;
b) receiving a request to perform a second
program while said first program is executing;
c) saving said processor status word, said
program counter value and data stored in said
register bank corresponding to said first program in
a designated location in said RAM via a dedicated
data bus and a dedicated address bus connecting said
executing unit of said microcomputer and said RAM;
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