Appeal No. 1997-2983 Page 3
Application No. 08/482,792
(e) a second bus for passing address data
corresponding to the data passed through said first
bus;
(f) a third bus for connecting said CPU
with said RAM, said third bus being used only for
passing data respectively held in said Program
Counter Register, said Processor Status Word
Register, and said General Purpose Register Set
between said CPU and said RAM, a number of bits of
said third bus being larger than that of said first
bus; and
(g) a fourth bus for connecting said CPU
with said RAM and passing address data corresponding
to said data passed through said third bus.
13. A microcomputer formed with a single chip,
comprising:
a system bus;
a random access memory formed within said single
chip and connected to said system bus, at least one
register bank being formed in said random access
memory;
an I/O device formed within said single chip and
connected to said system bus;
a CPU core formed within said single chip and
connected to said system bus for performing data
processing in cooperation with said random access
memory, said CPU core including an interface
controller for controlling data exchange through
said system bus, a decoder and control circuit for
decoding instructions to generate control signals,
an arithmetic logic unit for executing instructions,
a register file for providing temporary storage, a
bank pointer for indicating a location of said
register file in said random access memory, and an
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