Appeal No. 1997-2983 Page 4
Application No. 08/482,792
internal data bus through which data exchange is
performed among said interface controller, said
arithmetic logic unit and said register file;
an exclusive-use data bus connected between said
register file and said random access memory for data
exchange therebetween and provided separately from
said system bus; and
a bank address bus connected between said random
access memory and a bank pointer and provided
separately from said system bus for accessing said
random access memory to perform data transfer
between said register file and said random access
memory through said exclusive-use data bus.
Besides the appellants' admitted prior art (AAPA), the
references relied on in rejecting the claims follow:
Levy et al. (Levy) 3,999,163 Dec. 21,
1976
Delagi et al. (Delagi) 4,016,541 Apr. 5, 1977
Tanaka 4,733,346 Mar. 22, 1988
Maejima et al. (Maejima), "A 16-Bit Microprocessor
with Multi-Register Bank Architecture," 1986
Proceedings: Fall Joint Computer Conference, 1014-19
(1986).
Claims 1, 6, 11, 13, and 14 stand rejected under 35 U.S.C.
§ 103(a) as obvious over AAPA in view of Levy and Delagi.
Claims 2, 4, 7-10, and 12 stand rejected under 35 U.S.C. §
103(a) as obvious over AAPA in view of Levy and Delagi further
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