Appeal No. 1998-2924 Application NO. 08/276,290 The instant invention relates to a method of manufacturing an improved BiCMOS semiconductor device. Specifically, the invention is directed to a complementary metal oxide semiconductor (CMOS) memory architecture in which an auxiliary bipolar transistor structure is formed in a well region that is formed in common with a CMOS memory cell. Appellants' specification ("specification"), page 1, lines 1- 7. The auxiliary bipolar transistor structure is provided for the purpose of supplying a large magnitude current to enable programming of the memory cell. Specification, page 1, lines 15-20 to page 2, lines 1-4. The large current forced through the fusible links of a memory cell melts the fuse, severs the links, and forces the memory cell into a prescribed binary (1/0) condition. Specification, page 1, line 20 to page 2, line 4. The invention features the use of a separate implant mask for the emitter region of the auxiliary bipolar transistor. During the separate emitter formation step, the remainder of the substrate is masked, so that the emitter implant affects only the characteristics of the bipolar device. Specification, page 5. The geometry and impurity 2Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NextLast modified: November 3, 2007