Appeal No. 1998-2924
Application NO. 08/276,290
Appellants state that "the Examiner alleges that the
admitted prior art of [Appellants'] Figure 1 discloses
substantially the claimed process of forming first and second
well regions having the same depth." Brief, page 30. Next,
Appellants argue that it can be inferred from Tanabe that the
depths of the respective base and well regions are not the
same. Brief, page 31. Finally, Appellants argue that Sagara
teaches away from forming a base well having the same depth as
the well in which an adjacent MOS device was formed. Brief,
page 32.
In response, the Examiner points out that Appellants'
Figure 1 and the Background of the Invention illustrates base
and well regions of the same depth. Examiner's Answer, page
3. The Examiner already asserted in the Final Rejection,
Paper No. 17, that "[The] Background of the invention, pages
1-4 and related Fig. [figure] 1 discloses substantially the
claimed process for forming a programmable CMOS memory device
including the steps of forming first and second well regions
having the same depth
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