Appeal No. 1998-2924
Application NO. 08/276,290
concentration profile of the emitter region is tailored so
that the auxiliary transistor has sufficient current gain to
blow the fuse. Specification, page 4. Meanwhile, the doping
parameters of the source/drain regions of the CMOS structure
are separately established to maintain the integration density
of the memory and prevent thyristor latch-up. Specification,
page 4. During the implantation of the source/drain regions
in the CMOS well region, the well region in which the
auxiliary bipolar transistor is formed, is masked, so that no
emitter region is formed in the well region used for the
auxiliary bipolar transistor. Specification, page 5.
Appellants' independent claim 3, reproduced below, is
representative:
3. A method of manufacturing a semiconductor architecture
comprising the steps of:
(a) providing a semiconductor substrate of a first
conductivity type having a first surface;
(b) forming, to a first depth from said first surface in
respective first and second spaced-apart portions of said
semiconductor substrate, first and second well regions of
second conductivity type;
(c) forming first source and drain regions of said first
conductivity type of a first channel conductivity type MOS
structure in spaced apart surface portions of said first well
3
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