Appeal No. 1998-2924
Application NO. 08/276,290
. . . .” Now, the Examiner concludes that Appellants'
limitation has "been clearly disclosed and admitted as Prior
Art in the Background of the Invention." Examiner's Answer,
page 4.
We find that Appellants' claim 3 limitation of "forming,
to a first depth from said first surface in respective first
and second spaced-apart portions of said semiconductor
substrate, first and second well regions of second
conductivity type" is taught by Appellants' admitted prior art
as disclosed in Appellants' Specification, page 2, lines 5-16.
This section of the Specification recites in part,
A CMOS memory cell architecture . . . having a top
surface 13, in respective first and second spaced
portions 21 and 23 of which P-type well regions 31
and 33 are formed to a prescribed depth in substrate
11. (Emphasis added).
Specification, page 2, lines 1-12. Additionally, we find that
Appellants' Figure 1 illustrates the well regions 31 and 33
having a same depth.
Appellants do not traverse or otherwise dispute the
Examiner's contention that Appellants' admitted prior art does
teach the depth limitation. Appellants only argue that Tanabe
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