Appeal No. 1999-0259
Application 08/596,857
by the typical single lumped capacitor. Specification, page
10, lines 21-23. The effective load impedance of these cells
are more accurately modeled with an RC network (capacitor and
resistor combination). Specification, page 3, line 37 to page
4, lines 1-2. One embodiment of the present invention
features a data path having a plurality of serially coupled
transmission gate cells. Specification, page 9, lines 25-30.
In this
embodiment, distributed serial load models the effective load
impedance of the transmission gates with the RC network.
Specification, page 10, line 8-12. Yet another embodiment of
the present invention features a memory array comprising a
plurality of bit cells within a WORDLINE. Specification, page
6, lines 30-34. WORDLINE is modeled with a distributed serial
load and the RC load impedance network models the load of the
bit cell. Specification, page 7, lines 15-21.
Appellants’ independent claims encapsulate the
various embodiments of the invention. The independent
appealed claims 1, 10 and 16 are herein respectively recited:
1. A method of modeling loading of a plurality of
serially coupled circuit cells, comprising the steps of:
3
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