Ex parte MILLMAN et al. - Page 4




          Appeal No. 1999-0259                                                        
          Application 08/596,857                                                      



                    identifying effective load impedances for each of                 
          the plurality of serially coupled circuit cells where the                   
          circuit cells include active elements; and                                  
                    forming a distributed serial load with said                       
          effective load impedances where said distributed serial load                
          provides a load model of the plurality of serially coupled                  
          circuit cells.                                                              
                    10.       A method of simulating characteristics of a             
          plurality of serially coupled circuit cells, comprising the                 
          steps of:                                                                   



                    providing a first load for a first one of the                     
          plurality of serially coupled circuit cells where the circuit               
          cells include active elements;                                              
                    providing a second load for a second one of the                   
          plurality of serially coupled circuit cells where the circuit               
          cells include active elements; and                                          
                    forming a distributed serial load with said first                 
          and second loads of said first and second ones of the                       
          plurality of serially coupled circuit cells where said                      
          distributed serial load provides a characteristic load model                
          of the plurality of serially coupled circuit cells.                         
                    16.       A method of modeling a memory array                     
          comprising the steps of:                                                    
                    providing a first effective load impedance for a                  
          first bit cell of the memory array;                                         
                    providing a second effective load impedance for a                 
          second bit cell of the memory array; and                                    


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