Appeal No. 1999-1454 Page 10
Application No. 08/596,343
prior art (Figure 3), both the power transistor chip 2, along
with the control circuit 3 are mounted on metal insulating
plate 1. However, since conductive patterns 1c of metal
insulating plate 1 are used as a main circuit wiring
connection, it is necessary that a path width of conductive
pattern 1c be enlarged so as to obtain a desired electrical
capacitance. Hosen discloses (id.) that "the path width must
become larger as the electrical capacitance is increased."
This (page 2) leads to the desired area of the metal
insulating substrate to be increased, "leading to higher
cost." Hosen discloses (id.) that the object of the invention
is to "provide a power semiconductor device which has a small
area substrate and can sufficiently apply a large electrical
capacitance." In Figure 2, Hosen discloses (page 5) a two
stage stacking structure, leaving the high heat radiation
power chips 2 on the insulating metal layer 1, and placing the
control circuit 3, which have (page 6) "a calorific value
extremely smaller than the power chips 2," on substrate 8
which is above metal insulating layer 1. Hosen further
discloses that the metal control circuit substrate 8 is
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