Appeal No. 1999-1454 Page 11
Application No. 08/596,343
"formed in the same manner as the [metal insulating] substrate
1." Through the use of the aforementioned structure, Hosen
discloses (id.) that
The formation of a wide internal wiring pattern
on a copper foil of the substrate is not needed,
and the cross-sectional area of the terminal plate
can be freely selected in accordance with the
electrical capacitance of power chips. Therefore,
a power semiconductor device having a large electrical
capacitance can be constructed on a metal insulating
structure having a small area.
We thus find that the admitted prior art did not recognize
any problems associated with having all of the components on a
single multi-layer circuit wiring board. We further find that
Hosen is not directed to a CPU chip or CPU power converter,
and uses a two-stage stacking structure to avoid the use of a
wide internal wiring pattern in order to produce a power
semiconductor having a large electrical capacitance which can
be constructed on a metal insulating substrate having a small
area. Thus, we find Hosen's teaching of using a two-stage
stacking structure to provide a large electrical capacitance
to a small substrate area to be unrelated to any problem
associated with the single multi-layer circuit wiring board of
the admitted prior art.
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