Appeal No. 2000-1361 Page 2
Application No. 08/933,880
BACKGROUND
Appellant’s invention is directed to a synchronous circuit
with increased processing speed, which includes a combinatorial
block located between two registers. An analysis unit receives
and analyzes the value of the output of the input register to
determine when to send an enable signal to the output register
(specification, page 2). The analysis unit sends the enable
signal to the output register at the time the analysis unit
determines that an output value of the combinatorial blocks is
present, allowing the outcome to be taken earlier (specification,
page 4). Thus, based on the value combinations present at the
output of the input register, the outcome is clocked into the
output register sooner and the transit time required for
processing an operation through the combinatorial block is
decreased (abstract and specification, page 4).
Representative independent claim 1 is reproduced as follows:
1. A circuit arrangement with at least one
combinatorial block arranged between registers, comprising:
an input register of said registers having an output
connected to an input of the combinatorial block, and an
output register of said registers having an input connected
to an output of the combinatorial block; and
an analysis unit, the output of the input register also
connected to the analysis unit that analyzes a value of the
output of the input register and that sends an enable signal
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